utility gadget offers fast RTL To Silicon Design FlowThe Blast Chip IC implementation system takes an IC from RTL through remaining implementation. the usage of a single model right through the design flow, its brand says, it can optimize a whole design for the most beneficial timing and sign integrity outcomes without any iterations. subsequently, it vastly reduces the common sense and the actual design cycles.
The kit comprises the Blast Fusion actual design gadget. This function performs full chip design. It also sports a multimillion-gate means. Blast Fusion performs synthesis, logic optimization, clock, vigour and timing estimation, extraction and location and route, and signal integrity and congestion management. Designed to take full chips and massive designs from RTL through GDSII, clients can base partitioning on design or task management necessities, in preference to on tool means boundaries.
a few licensing alternate options can be found. every comes with a three-12 months, time-based mannequin. Blast Chip licenses start at $415,000 a 12 months. Blast Fusion licenses beginning at $385,000 a year. not obligatory licenses for Blast Noise, which prevents and corrects signal integrity complications, birth at $one hundred fifty,000 a year. All versions ship on Solaris and HP-UX workstations.
Magma Design Automation, 2 effects means, Cupertino, CA 95014; (408) 864-2000; fax (408) 864-2001; www.magma-da.com.
utility tool Generates Over 4000 system-certain I/O DevicesThe I/O Compiler application tool lets ASIC designers create an entire portfolio of method-specific I/O gadgets. users can choose from a large choice of points for each and every input, output, bidirectional, three-state, energy, and ground-pad type through its person-pleasant interface. These facets encompass pad pitches, operational voltages, voltage tolerances, and efficiency and testability alternate options. Its manufacturer says these facets give design flexibility and fine, producing a actual I/O design supported through main EDA equipment.
This tool has been silicon confirmed. it will possibly generate over 4000 distinct I/O devices according to the combination of elements selected. All I/Os conform to ESD and electrical guidelines, guaranteeing high yield and reliability. via helping the technology of front-conclusion design fashions and immediately imposing the physical returned-end views, the I/O Compiler shortens the product building cycle. additionally, it helps the 0.18-µm CMOS process while addressing analog and digital noise isolation issues.
Contact the company for pricing information.
Nurlogic Design Inc., 9710 Scranton Rd., Ste. 380, San Diego, CA 92121; (877) NURLOGIC, (619) 455-7570; fax (619) 457-5578; www.nurlogic.com.
Infrastructure makes it possible for far off Collaboration And ManagementCreOweb, an e-design/e-management infrastructure for net-primarily based, enterprise-to-enterprise engineering environments, lets far off designers collaborate in all engineering and administration phases. Its groupware options give the capability to entry and monitor physical databases through the internet. It features a powerful-server/thin-client architecture, hastens time-to-market, and eliminates costly handoffs and delays. a few crucial purposes are protected as smartly.
SiliconCruiser offers clients far off access to the lower back-end placement and routing counsel database each time, anywhere through any present browsers. GdsCruiser is an interactive layout viewer, while PackageCruiser is an IC packaging design viewer. DwgCruiser provides the fastest, most correct approach to view and distribute design drawings without the constraints of time, area, or availability of the drawing equipment. CreOx enables web-based, actual-time computing device software sharing. And, CreOflow conducts undertaking/movement administration.
Contact the enterprise for pricing and availability assistance.
CreOsys Inc., 39560 Stevenson Pl., Ste. 221, Fremont, CA 94539; (510) 796-1111; fax (510) 796-2445; www.creosys.com.
Design environment update Doubles Verilog Code coverage PerformanceThe Verification Navigator built-in design ambiance has been upgraded to version 6.1. Its new verify-suite optimization engine raises capability with the aid of over 100 times, enabling decreased simulation time for extremely giant regression look at various suites.
A extensive array of optimizations in the beginning focused on the most widespread coverage metrics have resulted in a dramatic enhance in Verilog code-insurance performance. compared with past models, version 6.1 has finished a normal of 2.three-fold lessen simulation overhead over a large number of designs.
Its VN-Optimize verify-suite optimization tool facets a very re-engineered optimization engine constructed to guide verify suites containing over 100,000 particular person look at various sets. This device also lets designers reduce examine simulation time via settling on redundant tests and by using sorting checks so as of their effectiveness.
Verification Navigator 6.1's base price begins at $20,000. existing clients beneath preservation will get hold of the new release for free of charge.
TransEDA, 985 college Ave., Los Gatos, CA 95032; (408) 907-2000; fax (408) 907-2085; www.transeda.com.
Standalone Verilog Simulator Meets IEEE 1364-ninety five StandardActive-HDL/VLOG, a standalone Verilog-compliant simulator, presents finished OVI compliance and PLI help in addition to seamless integration between design entry and simulation debugging application. Its Verilog simulation kernel, supported from inside the lively-HDL design ambiance, comprises Verilog design entry, testbench era, and high-performance direct collect Verilog simulation. constructed-in Verilog primitives provide quick bring together times and fast simulation as well.
This simulator absolutely supports the IEEE 1364-ninety five standard for compatibility with all current Verilog designs. Full programmable common sense interface, normal extend format, and cost change dump are supported as smartly. With this IEEE compliance, clients can simulate any design, design part, or IP core developed in any common HDL design device. active-HDL/VLOG also includes a project manager, an HDL editor, a state computer editor, a block diagram editor/schematic editor, and a waveform viewer and editor.
Pricing starts at $5200. Free evaluation copies can be found.
Aldec Inc., 2230 company Circle, Henderson, NV 89014; (800) 487-8743; fax (702) 990-4414; www.aldec.com.